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En kvantitativ studie av minnesbaserade schemaläggningstyper
University West, Department of Engineering Science, Division of Computer, Electrical and Surveying Engineering.
2015 (Swedish)Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesisAlternative title
A Quantitative Study of Memory-Based Scheduling Approaches (English)
Abstract [sv]

Processorer används idag i allt från smartphones till stora serverkluster och prestandakraven ökar ständigt. För att förbättra prestandan så ökar man antalet processorkärnor per processor, vilket leder till ett problem. De extra processorkärnorna genererar mer data till och från minnet, vilket leder till ökad belastning på den begränsade minnesbussen. Lösningen är att schemalägga program och därmed öka genomströmningen och undvika att minnesbussen blir överbelastad. En schemaläggare består av en algorittm och en karaktäriseringsmetod.Experimenten använde Slowdown based characterization, Miss rate, Stack distance competition och Solo memory bandwidth usage, vilket är fyra karaktäriseringsmetoder som kördes tillsammans med program från SPECint serien[1]. Syftet var att ta reda på hur metoderna presterade gentemot varandra samt om metodernas prestanda skiljde sig på olika datorsystem. [vänd dessa meningar, syfte först]Först skapades en baslinje genom att köra alla programkombinationer enskilt samt parvis. Efter det simulerades alla program med alla karakteriseringsmetoder som sedan kunde jämföras med baslinjen och således få ut hur karaktäriseringsmetoderna presterade.Karaktäriseringsmetoder som presterar bättre än medelvärdet av baslinjekörningarna är bra och har potential. PC1 hade 8,42% och PC2 6,10% i medelvärde. Slowdown based characterization fick på PC1 6,24% och på PC2 3,68% vilket gör den till den bästa karaktäriseringsmetoden. Solo memory bandwidth usage hade 7,25% på PC1 och 4,17% på PC2 vilket gör den till den näst bästa metoden. Miss rate var ojämn och hamnade på en tredje plats med 6,37% på PC1 och 6,45% på PC2. Stack distance competition blev den sämsta metoden med 10,51% på PC1 och 6,17% på PC2.

Abstract [en]

In today's society computer processors are used in everything from smartphones to big server clusters and performance demands are always increasing. To improve performance, additional cores are usually added to the processors but that leads to one problem. The added cores generates additional data traffic to the memory, which put strain on already bandwidth limited memory buss. To mitigate the problem, co-scheduling is used which leads to increased throughput and decreased strain on the memory bus. A co-scheduler contains two parts, an algorithm and a characterization method.The experiments used Slowdown based characterization, Miss rate, Stack distance competi-tion and Solo bandwidth usage, which is four characterization methods and they were co-scheduled togheter with programs from the SPECint suite[1]. The goal was to find out how the methods performed and if the performance was differ on different computer systems.The first step was to create a baseline by executing all programs individually and pairwise. When the baseline was finished all programs could be simulated against every characteriza-tion method. After that the characterization methods could be compared to the baseline executions to see how the characterization methods performed.The characterization methods, who performed better than the average of all the baseline executions are good and have potential. The average value was 8,42% on PC1 and 6,10% on PC2. The average value of the Slowdown based characterization method was 6,24% on PC1 and 3,68% on PC2, which makes it the best characterization method. Solo memory bandwidth usage had 7,25% on PC1 and 4,17% on PC2, which makes it the second best method. Miss rate performed unevenly and got the third place with an average value of 6,37% on PC1 and 6,45% on PC2. Stack distance competition was the worst method with 10,51% on PC1 and 6,17% on PC2.

Place, publisher, year, edition, pages
2015. , 29 p.
Keyword [en]
Processors, programs, co-scheduling, memory buss bandwidth
Keyword [sv]
Processorer, program, schemaläggning, minnesbussbandbredd
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:hv:diva-8312Local ID: EXD500OAI: oai:DiVA.org:hv-8312DiVA: diva2:857723
Subject / course
Computer enigeering
Educational program
Nätverksteknik
Supervisors
Examiners
Available from: 2015-09-30 Created: 2015-09-30 Last updated: 2015-09-30Bibliographically approved

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