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Addressing characterization methods for memory contention aware co-scheduling
University West, Department of Engineering Science, Division of Computer and Electrical Engineering.ORCID iD: 0000-0001-7232-0079
University West, Department of Engineering Science, Division of Computer and Electrical Engineering.ORCID iD: 0000-0003-0589-8086
2015 (English)In: Journal of Supercomputing, ISSN 0920-8542, E-ISSN 1573-0484, Vol. 71, no 4, 1451-1483 p.Article in journal (Refereed) Published
Abstract [en]

The ability to precisely predict how memory contention degrades performance when co-scheduling programs is critical for reaching high performance levels in cluster, grid and cloud environments. In this paper we present an overview and compare the performance of state-of-the-art characterization methods for memory aware (co-)scheduling. We evaluate the prediction accuracy and co-scheduling performance of four methods: one slowdown-based, two cache-contention based and one based on memory bandwidth usage. Both our regression analysis and scheduling simulations find that the slowdown based method, represented by Memgen, performs better than the other methods. The linear correlation coefficient (Formula presented.) of Memgen's prediction is 0.890. Memgen's preferred schedules reached 99.53 % of the obtainable performance on average. Also, the memory bandwidth usage method performed almost as well as the slowdown based method. Furthermore, while most prior work promote characterization based on cache miss rate we found it to be on par with random scheduling of programs and highly unreliable.

Place, publisher, year, edition, pages
2015. Vol. 71, no 4, 1451-1483 p.
Keyword [en]
Memory contention, Memory subsystem, Performance measurements, Co-scheduling, Slowdown based scheduling
National Category
Computer Science
Research subject
ENGINEERING, Computer engineering
Identifiers
URN: urn:nbn:se:hv:diva-7664DOI: 10.1007/s11227-014-1374-8Scopus ID: 2-s2.0-84939948746OAI: oai:DiVA.org:hv-7664DiVA: diva2:816172
Available from: 2015-06-02 Created: 2015-06-02 Last updated: 2017-12-04Bibliographically approved
In thesis
1. A Slowdown Prediction Method to Improve Memory Aware Scheduling
Open this publication in new window or tab >>A Slowdown Prediction Method to Improve Memory Aware Scheduling
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Scientific and technological advances in the area of integrated circuits have allowed the performance of microprocessors to grow exponentially since the late 1960's. However, the imbalance between processor and memory bus capacity has increased in recent years. The increasing on-chip-parallelism of multi-core processors has turned the memory subsystem into a key factor for achieving high performance. When two or more processes share the memory subsystem their execution times typically increase, even at relatively low levels of memory traffic. Current research shows that a throughput increase of up to 40% is possible if the job-scheduler can minimizes the slowdown caused by memory contention in industrial multi-core systems such as high performance clusters, datacenters or clouds. In order to optimize the throughput the job-scheduler has to know how much slower the process will execute when co-scheduled on the same server as other processes. Consequently, unless the slowdown is known, or can be fairly well estimated, the scheduling becomes pure guesswork and the performance suffers. The central question addressed in this thesis is how the slowdown caused by memory traffic interference between processes executing on the same server can be predicted and to what extent. This thesis presents and evaluates a new slowdown prediction method which estimates how much longer a program will execute when co-scheduled on the same multi-core server as another program. The method measures how external memory traffic affects a program by generating different levels of synthetic memory traffic while observing the change in execution time. Based on the observations it makes a first order prediction of how much slowdown the program will experience when exposed to external memory traffic. Experimental results show that the method's predictions correlate well with the real measured slowdowns. Furthermore, it is shown that scheduling based on the new slowdown prediction method yields a higher throughput than three other techniques suggested for avoiding co-scheduling slowdowns caused by memory contention. Finally, a novel scheme is suggested to avoid some of the worst co-schedules, thus increasing the system throughput.

Place, publisher, year, edition, pages
Göteborg: Chalmers University of Technology, 2016. 19 p.
Series
Doktorsavhandlingar vid Chalmers tekniska högskola, Ny serie, ISSN 0346-718X ; 4050
Keyword
Multi-core processor, slowdown aware scheduling, memory bandwidth, resource contention, last level cache, co-scheduling, performance evaluation
National Category
Computer Systems Information Systems, Social aspects
Research subject
ENGINEERING, Computer engineering
Identifiers
urn:nbn:se:hv:diva-9300 (URN)978-91-7597-369-2 (ISBN)
Public defence
2016-04-19, EC, Hörsalsvägen 11, Chalmers, Göteborg, 10:00 (English)
Opponent
Supervisors
Available from: 2016-04-07 Created: 2016-04-07 Last updated: 2016-04-07Bibliographically approved

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De Blanche, AndreasLundqvist, Thomas

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