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A methodology for estimating co-scheduling slowdowns due to memory bus contention on multicore nodes
University West, Department of Engineering Science, Division of Computer and Electrical Engineering. (PTW)ORCID iD: 0000-0001-7232-0079
University West, Department of Engineering Science, Division of Computer and Electrical Engineering. (PTW)ORCID iD: 0000-0003-0589-8086
2014 (English)In: Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2014, 2014, p. 216-223Conference paper, Published paper (Refereed)
Abstract [en]

When two or more programs are co-scheduled on the same multicore computer they might experience a slowdown due to the limited off-chip memory bandwidth. According to our measurements, this slowdown does not depend on the total bandwidth use in a simple way. One thing we observe is that a higher memory bandwidth usage will not always lead to a larger slowdown. This means that relying on bandwidth usage as input to a job scheduler might cause non-optimal scheduling of processes on multicore nodes in clusters, clouds, and grids. To guide scheduling decisions, we instead propose a slowdown based characterization approach. Real slowdowns are complex to measure due to the exponential number of experiments needed. Thus, we present a novel method for estimating the slowdown programs will experience when co-scheduled on the same computer. We evaluate the method by comparing the predictions made with real slowdown data and the often used memory bandwidth based method. This study show that a scheduler relying on slowdown based categorization makes fewer incorrect co-scheduling choices and the negative impact on program execution times is less than when using a bandwidth based categorization method.

Place, publisher, year, edition, pages
2014. p. 216-223
Keywords [en]
Cluster, cloud, multicore, memory bandwidth, co-scheduling, slowdown
National Category
Computer Sciences
Research subject
ENGINEERING, Computer engineering
Identifiers
URN: urn:nbn:se:hv:diva-6195DOI: 10.2316/P.2014.811-027Scopus ID: 2-s2.0-84898422321OAI: oai:DiVA.org:hv-6195DiVA, id: diva2:716028
Conference
12th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2014; Innsbruck; Austria; 17 February 2014 through 19 February 2014; Code 104419
Available from: 2014-05-07 Created: 2014-04-30 Last updated: 2018-01-11Bibliographically approved
In thesis
1. A Slowdown Prediction Method to Improve Memory Aware Scheduling
Open this publication in new window or tab >>A Slowdown Prediction Method to Improve Memory Aware Scheduling
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Scientific and technological advances in the area of integrated circuits have allowed the performance of microprocessors to grow exponentially since the late 1960's. However, the imbalance between processor and memory bus capacity has increased in recent years. The increasing on-chip-parallelism of multi-core processors has turned the memory subsystem into a key factor for achieving high performance. When two or more processes share the memory subsystem their execution times typically increase, even at relatively low levels of memory traffic. Current research shows that a throughput increase of up to 40% is possible if the job-scheduler can minimizes the slowdown caused by memory contention in industrial multi-core systems such as high performance clusters, datacenters or clouds. In order to optimize the throughput the job-scheduler has to know how much slower the process will execute when co-scheduled on the same server as other processes. Consequently, unless the slowdown is known, or can be fairly well estimated, the scheduling becomes pure guesswork and the performance suffers. The central question addressed in this thesis is how the slowdown caused by memory traffic interference between processes executing on the same server can be predicted and to what extent. This thesis presents and evaluates a new slowdown prediction method which estimates how much longer a program will execute when co-scheduled on the same multi-core server as another program. The method measures how external memory traffic affects a program by generating different levels of synthetic memory traffic while observing the change in execution time. Based on the observations it makes a first order prediction of how much slowdown the program will experience when exposed to external memory traffic. Experimental results show that the method's predictions correlate well with the real measured slowdowns. Furthermore, it is shown that scheduling based on the new slowdown prediction method yields a higher throughput than three other techniques suggested for avoiding co-scheduling slowdowns caused by memory contention. Finally, a novel scheme is suggested to avoid some of the worst co-schedules, thus increasing the system throughput.

Place, publisher, year, edition, pages
Göteborg: Chalmers University of Technology, 2016. p. 19
Series
Doktorsavhandlingar vid Chalmers tekniska högskola, Ny serie, ISSN 0346-718X ; 4050
Keywords
Multi-core processor, slowdown aware scheduling, memory bandwidth, resource contention, last level cache, co-scheduling, performance evaluation
National Category
Computer Systems Information Systems, Social aspects
Research subject
ENGINEERING, Computer engineering
Identifiers
urn:nbn:se:hv:diva-9300 (URN)978-91-7597-369-2 (ISBN)
Public defence
2016-04-19, EC, Hörsalsvägen 11, Chalmers, Göteborg, 10:00 (English)
Opponent
Supervisors
Available from: 2016-04-07 Created: 2016-04-07 Last updated: 2016-04-07Bibliographically approved

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De Blanche, AndreasLundqvist, Thomas

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