Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Graph matching constraints for synthesis with complex components
Lund University, Lund, Sweden.ORCID iD: 0000-0002-1748-8837
Lund University, Lund, Sweden.
2007 (English)In: 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) / [ed] Hana Kubatova, Lubeck, Germany, 2007Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we present a new method for high-level synthesis that enhances design flexibility, specialization and performance primarily conceived for programmable hardware. New programmable hardware devices often provide fast dedicated components that perform complex computations. Arbitrary complex computations can be efficiently extracted from the CDFG using our new graph matching constraint to produce final implementations that better suit the design to the targeted architecture. Our algorithm also reduces possible syntactic variances detecting semantically equivalent structures in the graph. This new graph matching constraint was integrated in our own Constraint Programming solver engine together with other constraints to naturally model the heterogeneous features present in the synthesis problem. The use of complex functional modules is taken into account in the optimization process during binding and scheduling yielding significantly shorter schedules and gains in terms of area and performance. We demonstrate our technique on a variety of HLS benchmarks and show that efficient design space exploration can be accomplished using this technique.

Place, publisher, year, edition, pages
Lubeck, Germany, 2007.
Keywords [en]
Hardware, Space exploration, Adders, High level synthesis, Computer architecture, Processor scheduling, Computer science, Engines, Performance gain, Process control
National Category
Information Systems, Social aspects
Research subject
SOCIAL SCIENCE, Informatics
Identifiers
URN: urn:nbn:se:hv:diva-13888DOI: 10.1109/DSD.2007.4341482ISBN: 0-7695-2978-X (electronic)OAI: oai:DiVA.org:hv-13888DiVA, id: diva2:1318666
Conference
10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)
Available from: 2019-05-28 Created: 2019-05-28 Last updated: 2019-08-20Bibliographically approved

Open Access in DiVA

No full text in DiVA

Other links

Publisher's full text

Search in DiVA

By author/editor
Fuentes, Ana
Information Systems, Social aspects

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 24 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf