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Method for Experimental Measurement of an Applications Memory Bus Usage
Högskolan Väst, Institutionen för ekonomi och it, Avd för datavetenskap och informatik.ORCID-id: 0000-0001-7232-0079
Högskolan Väst, Institutionen för ekonomi och it, Avd för datavetenskap och informatik. Högskolan Väst, Institutionen för teknik, matematik och datavetenskap, Avd för datavetenskap.
2010 (Engelska)Ingår i:   / [ed] Hamid Arabnia, CSREA Press , 2010Konferensbidrag, Publicerat paper (Refereegranskat)
Abstract [en]

The disproportion between processor and memory bus capacities has increased constantly during the last decades. With the introduction of multi-core processors the memory bus capacity is divided between the simultaneously executing processes (cores). The memory bus capacity directly affects the number of applications that can be executed simultaneously at its full potential. Thus, against this backdrop it becomes important to estimate how the limitation of the memory bus effects the applications performance. Towards this end we introduce a method and a tool for experimental estimation of an applications memory requirement as well as the impact of sharing the memory bus has on the execution times. The tool enables black-box approximate profiling of an applications memory bus usage during execution. It executes entirely in user-space and does not require access to the application code, only the binary. 

Ort, förlag, år, upplaga, sidor
CSREA Press , 2010.
Nyckelord [en]
Memory, experimental measurement, Multi-core, tool, prediction
Nationell ämneskategori
Datorteknik
Forskningsämne
TEKNIK, Datateknik
Identifikatorer
URN: urn:nbn:se:hv:diva-2445OAI: oai:DiVA.org:hv-2445DiVA, id: diva2:317185
Konferens
The 2010 International Conference on Parallel and Distributed Processing Techniques and Applications
Tillgänglig från: 2010-05-03 Skapad: 2010-05-03 Senast uppdaterad: 2020-04-02Bibliografiskt granskad
Ingår i avhandling
1. A Slowdown Prediction Method to Improve Memory Aware Scheduling
Öppna denna publikation i ny flik eller fönster >>A Slowdown Prediction Method to Improve Memory Aware Scheduling
2016 (Engelska)Doktorsavhandling, sammanläggning (Övrigt vetenskapligt)
Abstract [en]

Scientific and technological advances in the area of integrated circuits have allowed the performance of microprocessors to grow exponentially since the late 1960's. However, the imbalance between processor and memory bus capacity has increased in recent years. The increasing on-chip-parallelism of multi-core processors has turned the memory subsystem into a key factor for achieving high performance. When two or more processes share the memory subsystem their execution times typically increase, even at relatively low levels of memory traffic. Current research shows that a throughput increase of up to 40% is possible if the job-scheduler can minimizes the slowdown caused by memory contention in industrial multi-core systems such as high performance clusters, datacenters or clouds. In order to optimize the throughput the job-scheduler has to know how much slower the process will execute when co-scheduled on the same server as other processes. Consequently, unless the slowdown is known, or can be fairly well estimated, the scheduling becomes pure guesswork and the performance suffers. The central question addressed in this thesis is how the slowdown caused by memory traffic interference between processes executing on the same server can be predicted and to what extent. This thesis presents and evaluates a new slowdown prediction method which estimates how much longer a program will execute when co-scheduled on the same multi-core server as another program. The method measures how external memory traffic affects a program by generating different levels of synthetic memory traffic while observing the change in execution time. Based on the observations it makes a first order prediction of how much slowdown the program will experience when exposed to external memory traffic. Experimental results show that the method's predictions correlate well with the real measured slowdowns. Furthermore, it is shown that scheduling based on the new slowdown prediction method yields a higher throughput than three other techniques suggested for avoiding co-scheduling slowdowns caused by memory contention. Finally, a novel scheme is suggested to avoid some of the worst co-schedules, thus increasing the system throughput.

Ort, förlag, år, upplaga, sidor
Göteborg: Chalmers University of Technology, 2016. s. 19
Serie
Doktorsavhandlingar vid Chalmers tekniska högskola, Ny serie, ISSN 0346-718X ; 4050
Nyckelord
Multi-core processor, slowdown aware scheduling, memory bandwidth, resource contention, last level cache, co-scheduling, performance evaluation
Nationell ämneskategori
Datorsystem Systemvetenskap, informationssystem och informatik med samhällsvetenskaplig inriktning
Forskningsämne
TEKNIK, Datateknik
Identifikatorer
urn:nbn:se:hv:diva-9300 (URN)978-91-7597-369-2 (ISBN)
Disputation
2016-04-19, EC, Hörsalsvägen 11, Chalmers, Göteborg, 10:00 (Engelska)
Opponent
Handledare
Tillgänglig från: 2016-04-07 Skapad: 2016-04-07 Senast uppdaterad: 2019-01-04Bibliografiskt granskad

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de Blanche, AndreasMankefors-Christiernin, Stefan

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