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Dual-core efficiency for engineering simulation applications
Högskolan Väst, Institutionen för ekonomi och it, Avd för datavetenskap och informatik.ORCID-id: 0000-0001-7232-0079
Högskolan Väst, Institutionen för ekonomi och it, Avd för datavetenskap och informatik.
Högskolan Väst, Institutionen för ekonomi och it, Avd för datavetenskap och informatik.
Högskolan Väst, Institutionen för ekonomi och it, Avd för datavetenskap och informatik.
Visa övriga samt affilieringar
2008 (Engelska)Ingår i: 2008 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2008: Las Vegas, NV; 14 July 2008 through 17 July 2008, 2008, s. 962-968Konferensbidrag, Publicerat paper (Refereegranskat)
Ort, förlag, år, upplaga, sidor
2008. s. 962-968
Nationell ämneskategori
Systemvetenskap, informationssystem och informatik
Forskningsämne
TEKNIK, Datateknik
Identifikatorer
URN: urn:nbn:se:hv:diva-1513ISBN: 9781601320841 (tryckt)OAI: oai:DiVA.org:hv-1513DiVA, id: diva2:216576
Tillgänglig från: 2009-05-11 Skapad: 2009-05-11 Senast uppdaterad: 2019-01-04Bibliografiskt granskad
Ingår i avhandling
1. A Slowdown Prediction Method to Improve Memory Aware Scheduling
Öppna denna publikation i ny flik eller fönster >>A Slowdown Prediction Method to Improve Memory Aware Scheduling
2016 (Engelska)Doktorsavhandling, sammanläggning (Övrigt vetenskapligt)
Abstract [en]

Scientific and technological advances in the area of integrated circuits have allowed the performance of microprocessors to grow exponentially since the late 1960's. However, the imbalance between processor and memory bus capacity has increased in recent years. The increasing on-chip-parallelism of multi-core processors has turned the memory subsystem into a key factor for achieving high performance. When two or more processes share the memory subsystem their execution times typically increase, even at relatively low levels of memory traffic. Current research shows that a throughput increase of up to 40% is possible if the job-scheduler can minimizes the slowdown caused by memory contention in industrial multi-core systems such as high performance clusters, datacenters or clouds. In order to optimize the throughput the job-scheduler has to know how much slower the process will execute when co-scheduled on the same server as other processes. Consequently, unless the slowdown is known, or can be fairly well estimated, the scheduling becomes pure guesswork and the performance suffers. The central question addressed in this thesis is how the slowdown caused by memory traffic interference between processes executing on the same server can be predicted and to what extent. This thesis presents and evaluates a new slowdown prediction method which estimates how much longer a program will execute when co-scheduled on the same multi-core server as another program. The method measures how external memory traffic affects a program by generating different levels of synthetic memory traffic while observing the change in execution time. Based on the observations it makes a first order prediction of how much slowdown the program will experience when exposed to external memory traffic. Experimental results show that the method's predictions correlate well with the real measured slowdowns. Furthermore, it is shown that scheduling based on the new slowdown prediction method yields a higher throughput than three other techniques suggested for avoiding co-scheduling slowdowns caused by memory contention. Finally, a novel scheme is suggested to avoid some of the worst co-schedules, thus increasing the system throughput.

Ort, förlag, år, upplaga, sidor
Göteborg: Chalmers University of Technology, 2016. s. 19
Serie
Doktorsavhandlingar vid Chalmers tekniska högskola, Ny serie, ISSN 0346-718X ; 4050
Nyckelord
Multi-core processor, slowdown aware scheduling, memory bandwidth, resource contention, last level cache, co-scheduling, performance evaluation
Nationell ämneskategori
Datorsystem Systemvetenskap, informationssystem och informatik med samhällsvetenskaplig inriktning
Forskningsämne
TEKNIK, Datateknik
Identifikatorer
urn:nbn:se:hv:diva-9300 (URN)978-91-7597-369-2 (ISBN)
Disputation
2016-04-19, EC, Hörsalsvägen 11, Chalmers, Göteborg, 10:00 (Engelska)
Opponent
Handledare
Tillgänglig från: 2016-04-07 Skapad: 2016-04-07 Senast uppdaterad: 2019-01-04Bibliografiskt granskad

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Boklund, Andreas

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Boklund, AndreasNamaki, NimaMankefors-Christiernin, Stefan
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